The Set/Reset Latch component—a single-bit edge-triggered data storage. The following logic applies to the false-to-true transition of S or R:
- If S goes true and R does not change, then Out is true and remains true.
- If R goes true and S does not change, then Out is false and remains false.
- If both S and R go true on the same scan, then Out is false and remains false.
The SRLatch component has the following slots:
- Status: shows the component's status;
- Out: provides the actual latched value that is captured from the input property at the latch time. Link to this property to display the value on a graphic or to process the value with another component;
- Set: the Boolean property determining the Out value, depending on the Reset value;
- Reset: the Boolean property determining the Out value, depending on the Set value;
- Clock: the Boolean property that has either a true or false state for all latch components. This property latches the input property to the output property on the rising edge of input. This means that a single input property is captured and sent to the output property at the instant that the Clock status changes from false to true state, and NOT when the property changes from true to false state.