Module Registers | iC Knowledge Base

Registered Access

Modbus Address	Decimal Address	Hex Address	Register Name	Access	Description
30001	0	0x00	Version/Type	Read	Version and type of the device
30002	1	0x01	Address	Read	Module address
40003	2	0x02	Baud Rate	Read/write	Transmission speed
40004	3	0x03	Stop Bits	Read/write	Stop bits
40005	4	0x04	Parity	Read/write	Parity
40007	6	0x06	Modbus Mode	Read/write	Modbus protocol type
40009	8	0x08	Watchdog	Read/write	Function watchdog for outputs [ms]
40013	12	0x0C	Default Outputs State	Read/write	Default state of outputs
40014	13	0x0D	Operating Mode	Read/write	Modbus mode TCP0 – Device Table; 1 – Gateway Modbus TCP
40015	14	0x0E	Slow Rate	Read/write	Frequency of queries in Device Table mode [ms]
40016	15	0x0F	Normal Rate	Read/write	Frequency of queries in Device Table mode [ms]
40017	16	0x10	Fast Rate	Read/write	Frequency of queries in Device Table mode [ms]
40033	32	0x20	Received Packets LSR (Least Significant Register)	Read/write	The amount of received packets
40034	33	0x21	Received Packets MSR (Most Significant Register)	Read/write	The amount of received packets
40035	34	0x22	Incorrect Packets LSR	Read/write	The amount of received incorrect packets
40036	35	0x23	Incorrect Packets MSR	Read/write	The amount of received incorrect packets
40037	36	0x24	Sent Packets LSR	Read/write	The amount of sent packets
40038	37	0x25	Sent Packets MSR	Read/write	The amount of sent packets
30051	50	0x32	Inputs	Read	Inputs status lit bit → input active
40052	51	0x33	Outputs	Read/write	Outputs status
40053	52	0x34	Counter 0 LSR	Read/write	32-bits counter 0
40054	53	0x35	Counter 0 MSR	Read/write	32-bits counter 0
40055	54	0x36	Counter 1 LSR	Read/write	32-bits counter 1
40056	55	0x37	Counter 1 MSR	Read/write	32-bits counter 1
40057	56	0x38	Counter 2 LSR	Read/write	32-bits counter 2
40058	57	0x39	Counter 2 MSR	Read/write	32-bits counter 2
40059	58	0x3A	Counter 3 LSR	Read/write	32-bits counter 3
40060	59	0x3B	Counter 3 MSR	Read/write	32-bits counter 3
40061	60	0x3C	Reset Counters	Read/write	Reset counterslit bit → counter reset

Registered access

Bit Access

Modbus Addess	Decimal Address	Hex Address	Register Name	Access	Description
193	192	0x0C0	Default State of Output 1	Read/write	Default state of output 1
194	193	0x0C1	Default State of Output 2	Read/write	Default state of output 2
195	194	0x0C2	Default State of Output 3	Read/write	Default state of output 3
801	800	0x320	Input 1	Read	Input 1 state
802	801	0x321	Input 2	Read	Input 2 state
803	802	0x322	Input 3	Read	Input 3 state
804	803	0x323	Input 4	Read	Input 4 state
817	816	0x332	Digital Output 1	Read/write	State of digital output 1
818	817	0x333	Digital Output 2	Read/write	State of digital output 2
819	818	0x334	Digital Output 3	Read/write	State of digital output 3
962	961	0x3E0	Reset Counter 0	Read/write	Reset counter 0
963	962	0x3E1	Reset Counter 1	Read/write	Reset counter 1
964	963	0x3E2	Reset Counter 2	Read/write	Reset counter 2
965	964	0x3E3	Reset Counter 3	Read/write	Reset counter 3

Bit access